    cpldfit:  version L.33                              Xilinx Inc.
                                      Fitter Report
    Design Name: mdrive2                             Date:  6-13-2012,  7:32PM
    Device Used: XC9572-15-PC44
    Fitting Status: Successful

    *************************  Mapped Resource Summary  **************************

    Macrocells     Product Terms    Function Block   Registers      Pins
    Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot
    30 /72  ( 42%) 68  /360  ( 19%) 41 /144 ( 28%)   26 /72  ( 36%) 7  /34  ( 21%)

    ** Function Block Resources **

    Function    Mcells      FB Inps     Signals     Pterms      IO
    Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot
    FB1          14/18       13/36       13          26/90       0/ 9
    FB2           0/18        0/36        0           0/90       0/ 9
    FB3          16/18       28/36       28          42/90       4/ 8
    FB4           0/18        0/36        0           0/90       0/ 8
                 -----       -----                   -----       -----
                 30/72       41/144                  68/360      4/34

    * - Resource is exhausted

    ** Global Control Resources **

    Signal 'CLK' mapped onto global clock net GCK1.
    Global output enable net(s) unused.
    Global set/reset net(s) unused.

    ** Pin Resources **

    Signal Type    Required     Mapped  |  Pin Type            Used    Total
    ------------------------------------|------------------------------------
    Input         :    2           2    |  I/O              :     6      28
    Output        :    4           4    |  GCK/IO           :     1       3
    Bidirectional :    0           0    |  GTS/IO           :     0       2
    GCK           :    1           1    |  GSR/IO           :     0       1
    GTS           :    0           0    |
    GSR           :    0           0    |
                     ----        ----
            Total      7           7

    ** Power Data **

    There are 30 macrocells in high performance mode (MCHP).
    There are 0 macrocells in low power mode (MCLP).
    End of Mapped Resource Summary
    **************************  Errors and Warnings  ***************************

    INFO:Cpld - Inferring BUFG constraint for signal 'CLK' based upon the LOC
       constraint 'P5'. It is recommended that you declare this BUFG explicitedly in
       your design. Note that for certain device families the output of a BUFG
       constraint can not drive a gated clock, and the BUFG constraint will be
       ignored.
    *************************  Summary of Mapped Logic  ************************

    ** 4 Outputs **

    Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
    Name                Pts   Inps          No.  Type    Use     Mode Rate State
    m1                  5     11    FB3_8   13   I/O     O       STD  FAST
    m2                  5     11    FB3_9   14   I/O     O       STD  FAST
    m3                  4     11    FB3_11  18   I/O     O       STD  FAST
    m4                  4     11    FB3_14  19   I/O     O       STD  FAST

    ** 26 Buried Nodes **

    Signal              Total Total Loc     Pwr  Reg Init
    Name                Pts   Inps          Mode State
    ADD<0>              1     1     FB1_5   STD  RESET
    ADC<0>              1     1     FB1_6   STD  RESET
    ADD<6>              2     7     FB1_7   STD  RESET
    ADD<5>              2     6     FB1_8   STD  RESET
    ADD<4>              2     5     FB1_9   STD  RESET
    ADD<3>              2     4     FB1_10  STD  RESET
    ADD<2>              2     3     FB1_11  STD  RESET
    ADD<1>              2     2     FB1_12  STD  RESET
    ADC<6>              2     7     FB1_13  STD  RESET
    ADC<5>              2     6     FB1_14  STD  RESET
    ADC<4>              2     5     FB1_15  STD  RESET
    ADC<3>              2     4     FB1_16  STD  RESET
    ADC<2>              2     3     FB1_17  STD  RESET
    ADC<1>              2     2     FB1_18  STD  RESET
    ADD<9>              2     10    FB3_3   STD  RESET
    ADD<8>              2     9     FB3_4   STD  RESET
    ADD<7>              2     8     FB3_5   STD  RESET
    ADD<12>             2     13    FB3_6   STD  RESET
    ADD<11>             2     12    FB3_7   STD  RESET
    ADD<10>             2     11    FB3_10  STD  RESET
    ADC<9>              2     10    FB3_12  STD  RESET
    ADC<8>              2     9     FB3_13  STD  RESET
    ADC<7>              2     8     FB3_15  STD  RESET
    ADC<12>             2     13    FB3_16  STD  RESET
    ADC<11>             2     12    FB3_17  STD  RESET
    ADC<10>             2     11    FB3_18  STD  RESET

    ** 3 Inputs **

    Signal              Loc     Pin  Pin     Pin
    Name                        No.  Type    Use
    CLK                 FB1_9   5    GCK/I/O GCK
    PWM                 FB3_15  20   I/O     I
    CWCCW               FB3_17  22   I/O     I

    Legend:
    Pin No. - ~ - User Assigned
    **************************  Function Block Details  ************************
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
                   The number of Signals Used may exceed the number of FB Inputs
                   Used due to wire-ANDing in the switch matrix.
    Pin No.      - ~  - User Assigned
    *********************************** FB1  ***********************************
    Number of function block inputs used/remaining:               13/23
    Number of signals used by logic mapping into function block:  13
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0     0   5     FB1_1         (b)
    (unused)              0       0     0   5     FB1_2   1     I/O
    (unused)              0       0     0   5     FB1_3         (b)
    (unused)              0       0     0   5     FB1_4         (b)
    ADD<0>                1       0     0   4     FB1_5   2     I/O     (b)
    ADC<0>                1       0     0   4     FB1_6   3     I/O     (b)
    ADD<6>                2       0     0   3     FB1_7         (b)     (b)
    ADD<5>                2       0     0   3     FB1_8   4     I/O     (b)
    ADD<4>                2       0     0   3     FB1_9   5     GCK/I/O GCK
    ADD<3>                2       0     0   3     FB1_10        (b)     (b)
    ADD<2>                2       0     0   3     FB1_11  6     GCK/I/O (b)
    ADD<1>                2       0     0   3     FB1_12        (b)     (b)
    ADC<6>                2       0     0   3     FB1_13        (b)     (b)
    ADC<5>                2       0     0   3     FB1_14  7     GCK/I/O (b)
    ADC<4>                2       0     0   3     FB1_15  8     I/O     (b)
    ADC<3>                2       0     0   3     FB1_16        (b)     (b)
    ADC<2>                2       0     0   3     FB1_17  9     I/O     (b)
    ADC<1>                2       0     0   3     FB1_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: ADC<0>.LFBK        6: ADC<5>.LFBK       10: ADD<3>.LFBK
      2: ADC<1>.LFBK        7: ADD<0>.LFBK       11: ADD<4>.LFBK
      3: ADC<2>.LFBK        8: ADD<1>.LFBK       12: ADD<5>.LFBK
      4: ADC<3>.LFBK        9: ADD<2>.LFBK       13: PWM
      5: ADC<4>.LFBK

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    ADD<0>               ............X........................... 1       1
    ADC<0>               ............X........................... 1       1
    ADD<6>               ......XXXXXXX........................... 7       7
    ADD<5>               ......XXXXX.X........................... 6       6
    ADD<4>               ......XXXX..X........................... 5       5
    ADD<3>               ......XXX...X........................... 4       4
    ADD<2>               ......XX....X........................... 3       3
    ADD<1>               ......X.....X........................... 2       2
    ADC<6>               XXXXXX......X........................... 7       7
    ADC<5>               XXXXX.......X........................... 6       6
    ADC<4>               XXXX........X........................... 5       5
    ADC<3>               XXX.........X........................... 4       4
    ADC<2>               XX..........X........................... 3       3
    ADC<1>               X...........X........................... 2       2
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB2  ***********************************
    Number of function block inputs used/remaining:               0/36
    Number of signals used by logic mapping into function block:  0
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0     0   5     FB2_1         (b)
    (unused)              0       0     0   5     FB2_2   35    I/O
    (unused)              0       0     0   5     FB2_3         (b)
    (unused)              0       0     0   5     FB2_4         (b)
    (unused)              0       0     0   5     FB2_5   36    I/O
    (unused)              0       0     0   5     FB2_6   37    I/O
    (unused)              0       0     0   5     FB2_7         (b)
    (unused)              0       0     0   5     FB2_8   38    I/O
    (unused)              0       0     0   5     FB2_9   39    GSR/I/O
    (unused)              0       0     0   5     FB2_10        (b)
    (unused)              0       0     0   5     FB2_11  40    GTS/I/O
    (unused)              0       0     0   5     FB2_12        (b)
    (unused)              0       0     0   5     FB2_13        (b)
    (unused)              0       0     0   5     FB2_14  42    GTS/I/O
    (unused)              0       0     0   5     FB2_15  43    I/O
    (unused)              0       0     0   5     FB2_16        (b)
    (unused)              0       0     0   5     FB2_17  44    I/O
    (unused)              0       0     0   5     FB2_18        (b)
    *********************************** FB3  ***********************************
    Number of function block inputs used/remaining:               28/8
    Number of signals used by logic mapping into function block:  28
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0     0   5     FB3_1         (b)
    (unused)              0       0     0   5     FB3_2   11    I/O
    ADD<9>                2       0     0   3     FB3_3         (b)     (b)
    ADD<8>                2       0     0   3     FB3_4         (b)     (b)
    ADD<7>                2       0     0   3     FB3_5   12    I/O     (b)
    ADD<12>               2       0     0   3     FB3_6         (b)     (b)
    ADD<11>               2       0     0   3     FB3_7         (b)     (b)
    m1                    5       0     0   0     FB3_8   13    I/O     O
    m2                    5       0     0   0     FB3_9   14    I/O     O
    ADD<10>               2       0     0   3     FB3_10        (b)     (b)
    m3                    4       0     0   1     FB3_11  18    I/O     O
    ADC<9>                2       0     0   3     FB3_12        (b)     (b)
    ADC<8>                2       0     0   3     FB3_13        (b)     (b)
    m4                    4       0     0   1     FB3_14  19    I/O     O
    ADC<7>                2       0     0   3     FB3_15  20    I/O     I
    ADC<12>               2       0     0   3     FB3_16        (b)     (b)
    ADC<11>               2       0     0   3     FB3_17  22    I/O     I
    ADC<10>               2       0     0   3     FB3_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: ADC<0>            11: ADC<7>.LFBK       20: ADD<3>
      2: ADC<10>.LFBK      12: ADC<8>.LFBK       21: ADD<4>
      3: ADC<11>.LFBK      13: ADC<9>.LFBK       22: ADD<5>
      4: ADC<12>.LFBK      14: ADD<0>            23: ADD<6>
      5: ADC<1>            15: ADD<10>.LFBK      24: ADD<7>.LFBK
      6: ADC<2>            16: ADD<11>.LFBK      25: ADD<8>.LFBK
      7: ADC<3>            17: ADD<12>.LFBK      26: ADD<9>.LFBK
      8: ADC<4>            18: ADD<1>            27: CWCCW
      9: ADC<5>            19: ADD<2>            28: PWM
     10: ADC<6>

    Signal                        1         2         3         4 Signals FB
    Name                0----+----0----+----0----+----0----+----0 Used    Inputs
    ADD<9>               .............X...XXXXXXXX..X............ 10      10
    ADD<8>               .............X...XXXXXXX...X............ 9       9
    ADD<7>               .............X...XXXXXX....X............ 8       8
    ADD<12>              .............XXX.XXXXXXXXX.X............ 13      13
    ADD<11>              .............XX..XXXXXXXXX.X............ 12      12
    m1                   ..............XXX...XXXXXXXX............ 11      11
    m2                   ..............XXX...XXXXXXXX............ 11      11
    ADD<10>              .............X...XXXXXXXXX.X............ 11      11
    m3                   .XXX...XXXXXX.............XX............ 11      11
    ADC<9>               X...XXXXXXXX...............X............ 10      10
    ADC<8>               X...XXXXXXX................X............ 9       9
    m4                   .XXX...XXXXXX.............XX............ 11      11
    ADC<7>               X...XXXXXX.................X............ 8       8
    ADC<12>              XXX.XXXXXXXXX..............X............ 13      13
    ADC<11>              XX..XXXXXXXXX..............X............ 12      12
    ADC<10>              X...XXXXXXXXX..............X............ 11      11
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB4  ***********************************
    Number of function block inputs used/remaining:               0/36
    Number of signals used by logic mapping into function block:  0
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0     0   5     FB4_1         (b)
    (unused)              0       0     0   5     FB4_2   24    I/O
    (unused)              0       0     0   5     FB4_3         (b)
    (unused)              0       0     0   5     FB4_4         (b)
    (unused)              0       0     0   5     FB4_5   25    I/O
    (unused)              0       0     0   5     FB4_6         (b)
    (unused)              0       0     0   5     FB4_7         (b)
    (unused)              0       0     0   5     FB4_8   26    I/O
    (unused)              0       0     0   5     FB4_9   27    I/O
    (unused)              0       0     0   5     FB4_10        (b)
    (unused)              0       0     0   5     FB4_11  28    I/O
    (unused)              0       0     0   5     FB4_12        (b)
    (unused)              0       0     0   5     FB4_13        (b)
    (unused)              0       0     0   5     FB4_14  29    I/O
    (unused)              0       0     0   5     FB4_15  33    I/O
    (unused)              0       0     0   5     FB4_16        (b)
    (unused)              0       0     0   5     FB4_17  34    I/O
    (unused)              0       0     0   5     FB4_18        (b)
    *******************************  Equations  ********************************

    ********** Mapped Logic **********

    FTCPE_ADC0: FTCPE port map (ADC(0),'1',CLK,PWM,'0');

    FTCPE_ADC1: FTCPE port map (ADC(1),ADC(0).LFBK,CLK,PWM,'0');

    FTCPE_ADC2: FTCPE port map (ADC(2),ADC_T(2),CLK,PWM,'0');
    ADC_T(2) <= (ADC(0).LFBK AND ADC(1).LFBK);

    FTCPE_ADC3: FTCPE port map (ADC(3),ADC_T(3),CLK,PWM,'0');
    ADC_T(3) <= (ADC(0).LFBK AND ADC(1).LFBK AND ADC(2).LFBK);

    FTCPE_ADC4: FTCPE port map (ADC(4),ADC_T(4),CLK,PWM,'0');
    ADC_T(4) <= (ADC(0).LFBK AND ADC(1).LFBK AND ADC(2).LFBK AND
    	ADC(3).LFBK);

    FTCPE_ADC5: FTCPE port map (ADC(5),ADC_T(5),CLK,PWM,'0');
    ADC_T(5) <= (ADC(0).LFBK AND ADC(1).LFBK AND ADC(2).LFBK AND
    	ADC(3).LFBK AND ADC(4).LFBK);

    FTCPE_ADC6: FTCPE port map (ADC(6),ADC_T(6),CLK,PWM,'0');
    ADC_T(6) <= (ADC(0).LFBK AND ADC(1).LFBK AND ADC(2).LFBK AND
    	ADC(3).LFBK AND ADC(4).LFBK AND ADC(5).LFBK);

    FTCPE_ADC7: FTCPE port map (ADC(7),ADC_T(7),CLK,PWM,'0');
    ADC_T(7) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND
    	ADC(2) AND ADC(3));

    FTCPE_ADC8: FTCPE port map (ADC(8),ADC_T(8),CLK,PWM,'0');
    ADC_T(8) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND
    	ADC(2) AND ADC(3) AND ADC(7).LFBK);

    FTCPE_ADC9: FTCPE port map (ADC(9),ADC_T(9),CLK,PWM,'0');
    ADC_T(9) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND
    	ADC(2) AND ADC(3) AND ADC(7).LFBK AND ADC(8).LFBK);

    FTCPE_ADC10: FTCPE port map (ADC(10),ADC_T(10),CLK,PWM,'0');
    ADC_T(10) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND
    	ADC(2) AND ADC(3) AND ADC(7).LFBK AND ADC(8).LFBK AND
    	ADC(9).LFBK);

    FTCPE_ADC11: FTCPE port map (ADC(11),ADC_T(11),CLK,PWM,'0');
    ADC_T(11) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND
    	ADC(2) AND ADC(3) AND ADC(7).LFBK AND ADC(8).LFBK AND
    	ADC(9).LFBK AND ADC(10).LFBK);

    FTCPE_ADC12: FTCPE port map (ADC(12),ADC_T(12),CLK,PWM,'0');
    ADC_T(12) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND
    	ADC(2) AND ADC(3) AND ADC(7).LFBK AND ADC(8).LFBK AND
    	ADC(9).LFBK AND ADC(10).LFBK AND ADC(11).LFBK);

    FTCPE_ADD0: FTCPE port map (ADD(0),'1',CLK,NOT PWM,'0');

    FTCPE_ADD1: FTCPE port map (ADD(1),ADD(0).LFBK,CLK,NOT PWM,'0');

    FTCPE_ADD2: FTCPE port map (ADD(2),ADD_T(2),CLK,NOT PWM,'0');
    ADD_T(2) <= (ADD(0).LFBK AND ADD(1).LFBK);

    FTCPE_ADD3: FTCPE port map (ADD(3),ADD_T(3),CLK,NOT PWM,'0');
    ADD_T(3) <= (ADD(0).LFBK AND ADD(1).LFBK AND ADD(2).LFBK);

    FTCPE_ADD4: FTCPE port map (ADD(4),ADD_T(4),CLK,NOT PWM,'0');
    ADD_T(4) <= (ADD(0).LFBK AND ADD(1).LFBK AND ADD(2).LFBK AND
    	ADD(3).LFBK);

    FTCPE_ADD5: FTCPE port map (ADD(5),ADD_T(5),CLK,NOT PWM,'0');
    ADD_T(5) <= (ADD(0).LFBK AND ADD(1).LFBK AND ADD(2).LFBK AND
    	ADD(3).LFBK AND ADD(4).LFBK);

    FTCPE_ADD6: FTCPE port map (ADD(6),ADD_T(6),CLK,NOT PWM,'0');
    ADD_T(6) <= (ADD(0).LFBK AND ADD(1).LFBK AND ADD(2).LFBK AND
    	ADD(3).LFBK AND ADD(4).LFBK AND ADD(5).LFBK);

    FTCPE_ADD7: FTCPE port map (ADD(7),ADD_T(7),CLK,NOT PWM,'0');
    ADD_T(7) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND
    	ADD(2) AND ADD(3));

    FTCPE_ADD8: FTCPE port map (ADD(8),ADD_T(8),CLK,NOT PWM,'0');
    ADD_T(8) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND
    	ADD(2) AND ADD(3) AND ADD(7).LFBK);

    FTCPE_ADD9: FTCPE port map (ADD(9),ADD_T(9),CLK,NOT PWM,'0');
    ADD_T(9) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND
    	ADD(2) AND ADD(3) AND ADD(7).LFBK AND ADD(8).LFBK);

    FTCPE_ADD10: FTCPE port map (ADD(10),ADD_T(10),CLK,NOT PWM,'0');
    ADD_T(10) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND
    	ADD(2) AND ADD(3) AND ADD(7).LFBK AND ADD(8).LFBK AND
    	ADD(9).LFBK);

    FTCPE_ADD11: FTCPE port map (ADD(11),ADD_T(11),CLK,NOT PWM,'0');
    ADD_T(11) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND
    	ADD(2) AND ADD(3) AND ADD(7).LFBK AND ADD(8).LFBK AND
    	ADD(9).LFBK AND ADD(10).LFBK);

    FTCPE_ADD12: FTCPE port map (ADD(12),ADD_T(12),CLK,NOT PWM,'0');
    ADD_T(12) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND
    	ADD(2) AND ADD(3) AND ADD(7).LFBK AND ADD(8).LFBK AND
    	ADD(9).LFBK AND ADD(10).LFBK AND ADD(11).LFBK);

    m1 <= NOT (((NOT PWM)
    	OR (CWCCW)
    	OR (NOT ADD(7).LFBK AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND
    	NOT ADD(11).LFBK AND NOT ADD(12).LFBK)
    	OR (NOT ADD(8).LFBK AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND
    	NOT ADD(11).LFBK AND NOT ADD(12).LFBK)
    	OR (NOT ADD(4) AND NOT ADD(5) AND NOT ADD(6) AND NOT ADD(9).LFBK AND
    	NOT ADD(10).LFBK AND NOT ADD(11).LFBK AND NOT ADD(12).LFBK)));

    m2 <= NOT (((NOT PWM)
    	OR (NOT CWCCW)
    	OR (NOT ADD(7).LFBK AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND
    	NOT ADD(11).LFBK AND NOT ADD(12).LFBK)
    	OR (NOT ADD(8).LFBK AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND
    	NOT ADD(11).LFBK AND NOT ADD(12).LFBK)
    	OR (NOT ADD(4) AND NOT ADD(5) AND NOT ADD(6) AND NOT ADD(9).LFBK AND
    	NOT ADD(10).LFBK AND NOT ADD(11).LFBK AND NOT ADD(12).LFBK)));

    m3 <= ((PWM AND CWCCW)
    	OR (CWCCW AND NOT ADC(7).LFBK AND NOT ADC(9).LFBK AND
    	NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK)
    	OR (CWCCW AND NOT ADC(8).LFBK AND NOT ADC(9).LFBK AND
    	NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK)
    	OR (NOT ADC(4) AND NOT ADC(5) AND NOT ADC(6) AND CWCCW AND NOT ADC(9).LFBK AND
    	NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK));

    m4 <= ((PWM AND NOT CWCCW)
    	OR (NOT CWCCW AND NOT ADC(7).LFBK AND NOT ADC(9).LFBK AND
    	NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK)
    	OR (NOT CWCCW AND NOT ADC(8).LFBK AND NOT ADC(9).LFBK AND
    	NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK)
    	OR (NOT ADC(4) AND NOT ADC(5) AND NOT ADC(6) AND NOT CWCCW AND NOT ADC(9).LFBK AND
    	NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE);
     FTCPE (Q,D,C,CLR,PRE);
     LDCP  (Q,D,G,CLR,PRE);

    ******************************  Device Pin Out *****************************

    Device : XC9572-15-PC44

       --------------------------------
      /6  5  4  3  2  1  44 43 42 41 40 \
     | 7                             39 |
     | 8                             38 |
     | 9                             37 |
     | 10                            36 |
     | 11        XC9572-15-PC44      35 |
     | 12                            34 |
     | 13                            33 |
     | 14                            32 |
     | 15                            31 |
     | 16                            30 |
     | 17                            29 |
     \ 18 19 20 21 22 23 24 25 26 27 28 /
       --------------------------------

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 TIE                              23 GND
      2 TIE                              24 TIE
      3 TIE                              25 TIE
      4 TIE                              26 TIE
      5 CLK                              27 TIE
      6 TIE                              28 TIE
      7 TIE                              29 TIE
      8 TIE                              30 TDO
      9 TIE                              31 GND
     10 GND                              32 VCC
     11 TIE                              33 TIE
     12 TIE                              34 TIE
     13 m1                               35 TIE
     14 m2                               36 TIE
     15 TDI                              37 TIE
     16 TMS                              38 TIE
     17 TCK                              39 TIE
     18 m3                               40 TIE
     19 m4                               41 VCC
     20 PWM                              42 TIE
     21 VCC                              43 TIE
     22 CWCCW                            44 TIE

    Legend :  NC  = Not Connected, unbonded pin
             PGND = Unused I/O configured as additional Ground pin
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             VCC  = Dedicated Power Pin
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc9572-15-PC44
    Optimization Method                         : SPEED
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : FAST
    Power Mode                                  : STD
    Ground on Unused IOs                        : OFF
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    FASTConnect/UIM optimzation                 : ON
    Local Feedback                              : ON
    Pin Feedback                                : ON
    Input Limit                                 : 36
    Pterm Limit                                 : 25