### Equations

********** Mapped Logic **********
FTCPE_ADC0: FTCPE port map (ADC(0),'1',CLK,PWM,'0');
FTCPE_ADC1: FTCPE port map (ADC(1),ADC(0).LFBK,CLK,PWM,'0');
FTCPE_ADC2: FTCPE port map (ADC(2),ADC_T(2),CLK,PWM,'0'); ADC_T(2) <= (ADC(0).LFBK AND ADC(1).LFBK);
FTCPE_ADC3: FTCPE port map (ADC(3),ADC_T(3),CLK,PWM,'0'); ADC_T(3) <= (ADC(0).LFBK AND ADC(1).LFBK AND ADC(2).LFBK);
FTCPE_ADC4: FTCPE port map (ADC(4),ADC_T(4),CLK,PWM,'0'); ADC_T(4) <= (ADC(0).LFBK AND ADC(1).LFBK AND ADC(2).LFBK AND ADC(3).LFBK);
FTCPE_ADC5: FTCPE port map (ADC(5),ADC_T(5),CLK,PWM,'0'); ADC_T(5) <= (ADC(0).LFBK AND ADC(1).LFBK AND ADC(2).LFBK AND ADC(3).LFBK AND ADC(4).LFBK);
FTCPE_ADC6: FTCPE port map (ADC(6),ADC_T(6),CLK,PWM,'0'); ADC_T(6) <= (ADC(0).LFBK AND ADC(1).LFBK AND ADC(2).LFBK AND ADC(3).LFBK AND ADC(4).LFBK AND ADC(5).LFBK);
FTCPE_ADC7: FTCPE port map (ADC(7),ADC_T(7),CLK,PWM,'0'); ADC_T(7) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND ADC(2) AND ADC(3));
FTCPE_ADC8: FTCPE port map (ADC(8),ADC_T(8),CLK,PWM,'0'); ADC_T(8) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND ADC(2) AND ADC(3) AND ADC(7).LFBK);
FTCPE_ADC9: FTCPE port map (ADC(9),ADC_T(9),CLK,PWM,'0'); ADC_T(9) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND ADC(2) AND ADC(3) AND ADC(7).LFBK AND ADC(8).LFBK);
FTCPE_ADC10: FTCPE port map (ADC(10),ADC_T(10),CLK,PWM,'0'); ADC_T(10) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND ADC(2) AND ADC(3) AND ADC(7).LFBK AND ADC(8).LFBK AND ADC(9).LFBK);
FTCPE_ADC11: FTCPE port map (ADC(11),ADC_T(11),CLK,PWM,'0'); ADC_T(11) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND ADC(2) AND ADC(3) AND ADC(7).LFBK AND ADC(8).LFBK AND ADC(9).LFBK AND ADC(10).LFBK);
FTCPE_ADC12: FTCPE port map (ADC(12),ADC_T(12),CLK,PWM,'0'); ADC_T(12) <= (ADC(0) AND ADC(4) AND ADC(5) AND ADC(6) AND ADC(1) AND ADC(2) AND ADC(3) AND ADC(7).LFBK AND ADC(8).LFBK AND ADC(9).LFBK AND ADC(10).LFBK AND ADC(11).LFBK);
FTCPE_ADD0: FTCPE port map (ADD(0),'1',CLK,NOT PWM,'0');
FTCPE_ADD1: FTCPE port map (ADD(1),ADD(0).LFBK,CLK,NOT PWM,'0');
FTCPE_ADD2: FTCPE port map (ADD(2),ADD_T(2),CLK,NOT PWM,'0'); ADD_T(2) <= (ADD(0).LFBK AND ADD(1).LFBK);
FTCPE_ADD3: FTCPE port map (ADD(3),ADD_T(3),CLK,NOT PWM,'0'); ADD_T(3) <= (ADD(0).LFBK AND ADD(1).LFBK AND ADD(2).LFBK);
FTCPE_ADD4: FTCPE port map (ADD(4),ADD_T(4),CLK,NOT PWM,'0'); ADD_T(4) <= (ADD(0).LFBK AND ADD(1).LFBK AND ADD(2).LFBK AND ADD(3).LFBK);
FTCPE_ADD5: FTCPE port map (ADD(5),ADD_T(5),CLK,NOT PWM,'0'); ADD_T(5) <= (ADD(0).LFBK AND ADD(1).LFBK AND ADD(2).LFBK AND ADD(3).LFBK AND ADD(4).LFBK);
FTCPE_ADD6: FTCPE port map (ADD(6),ADD_T(6),CLK,NOT PWM,'0'); ADD_T(6) <= (ADD(0).LFBK AND ADD(1).LFBK AND ADD(2).LFBK AND ADD(3).LFBK AND ADD(4).LFBK AND ADD(5).LFBK);
FTCPE_ADD7: FTCPE port map (ADD(7),ADD_T(7),CLK,NOT PWM,'0'); ADD_T(7) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND ADD(2) AND ADD(3));
FTCPE_ADD8: FTCPE port map (ADD(8),ADD_T(8),CLK,NOT PWM,'0'); ADD_T(8) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND ADD(2) AND ADD(3) AND ADD(7).LFBK);
FTCPE_ADD9: FTCPE port map (ADD(9),ADD_T(9),CLK,NOT PWM,'0'); ADD_T(9) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND ADD(2) AND ADD(3) AND ADD(7).LFBK AND ADD(8).LFBK);
FTCPE_ADD10: FTCPE port map (ADD(10),ADD_T(10),CLK,NOT PWM,'0'); ADD_T(10) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND ADD(2) AND ADD(3) AND ADD(7).LFBK AND ADD(8).LFBK AND ADD(9).LFBK);
FTCPE_ADD11: FTCPE port map (ADD(11),ADD_T(11),CLK,NOT PWM,'0'); ADD_T(11) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND ADD(2) AND ADD(3) AND ADD(7).LFBK AND ADD(8).LFBK AND ADD(9).LFBK AND ADD(10).LFBK);
FTCPE_ADD12: FTCPE port map (ADD(12),ADD_T(12),CLK,NOT PWM,'0'); ADD_T(12) <= (ADD(0) AND ADD(4) AND ADD(5) AND ADD(6) AND ADD(1) AND ADD(2) AND ADD(3) AND ADD(7).LFBK AND ADD(8).LFBK AND ADD(9).LFBK AND ADD(10).LFBK AND ADD(11).LFBK);
m1 <= NOT (((NOT PWM) OR (CWCCW) OR (NOT ADD(7).LFBK AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND NOT ADD(11).LFBK AND NOT ADD(12).LFBK) OR (NOT ADD(8).LFBK AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND NOT ADD(11).LFBK AND NOT ADD(12).LFBK) OR (NOT ADD(4) AND NOT ADD(5) AND NOT ADD(6) AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND NOT ADD(11).LFBK AND NOT ADD(12).LFBK)));
m2 <= NOT (((NOT PWM) OR (NOT CWCCW) OR (NOT ADD(7).LFBK AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND NOT ADD(11).LFBK AND NOT ADD(12).LFBK) OR (NOT ADD(8).LFBK AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND NOT ADD(11).LFBK AND NOT ADD(12).LFBK) OR (NOT ADD(4) AND NOT ADD(5) AND NOT ADD(6) AND NOT ADD(9).LFBK AND NOT ADD(10).LFBK AND NOT ADD(11).LFBK AND NOT ADD(12).LFBK)));
m3 <= ((PWM AND CWCCW) OR (CWCCW AND NOT ADC(7).LFBK AND NOT ADC(9).LFBK AND NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK) OR (CWCCW AND NOT ADC(8).LFBK AND NOT ADC(9).LFBK AND NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK) OR (NOT ADC(4) AND NOT ADC(5) AND NOT ADC(6) AND CWCCW AND NOT ADC(9).LFBK AND NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK));
m4 <= ((PWM AND NOT CWCCW) OR (NOT CWCCW AND NOT ADC(7).LFBK AND NOT ADC(9).LFBK AND NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK) OR (NOT CWCCW AND NOT ADC(8).LFBK AND NOT ADC(9).LFBK AND NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK) OR (NOT ADC(4) AND NOT ADC(5) AND NOT ADC(6) AND NOT CWCCW AND NOT ADC(9).LFBK AND NOT ADC(10).LFBK AND NOT ADC(11).LFBK AND NOT ADC(12).LFBK));
Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE);