Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Power Mode Slew Rate Pin Number Pin Type Pin Use Reg Init State
ADD<0> 1 1 FB1 MC5 STD   2 I/O (b) RESET
ADC<0> 1 1 FB1 MC6 STD   3 I/O (b) RESET
ADD<5> 2 6 FB1 MC8 STD   4 I/O (b) RESET
ADD<4> 2 5 FB1 MC9 STD   5 I/O/GCK1 GCK RESET
ADD<2> 2 3 FB1 MC11 STD   6 I/O/GCK2 (b) RESET
ADC<5> 2 6 FB1 MC14 STD   7 I/O/GCK3 (b) RESET
ADC<4> 2 5 FB1 MC15 STD   8 I/O (b) RESET
ADC<2> 2 3 FB1 MC17 STD   9 I/O (b) RESET
ADD<7> 2 8 FB3 MC5 STD   12 I/O (b) RESET
m1 5 11 FB3 MC8 STD FAST 13 I/O O  
m2 5 11 FB3 MC9 STD FAST 14 I/O O  
m3 4 11 FB3 MC11 STD FAST 18 I/O O  
m4 4 11 FB3 MC14 STD FAST 19 I/O O  
ADC<7> 2 8 FB3 MC15 STD   20 I/O I RESET
ADC<11> 2 12 FB3 MC17 STD   22 I/O I RESET
ADD<6> 2 7 FB1 MC7 STD     (b) (b) T     RESET
ADD<3> 2 4 FB1 MC10 STD     (b) (b) T     RESET
ADD<1> 2 2 FB1 MC12 STD     (b) (b) T     RESET
ADC<6> 2 7 FB1 MC13 STD     (b) (b) T     RESET
ADC<3> 2 4 FB1 MC16 STD     (b) (b) T     RESET
ADC<1> 2 2 FB1 MC18 STD     (b) (b) T     RESET
ADD<9> 2 10 FB3 MC3 STD     (b) (b) T     RESET
ADD<8> 2 9 FB3 MC4 STD     (b) (b) T     RESET
ADD<12> 2 13 FB3 MC6 STD     (b) (b) T     RESET
ADD<11> 2 12 FB3 MC7 STD     (b) (b) T     RESET
ADD<10> 2 11 FB3 MC10 STD     (b) (b) T     RESET
ADC<9> 2 10 FB3 MC12 STD     (b) (b) T     RESET
ADC<8> 2 9 FB3 MC13 STD     (b) (b) T     RESET
ADC<12> 2 13 FB3 MC16 STD     (b) (b) T     RESET
ADC<10> 2 11 FB3 MC18 STD     (b) (b) T     RESET