Timing Report

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Design Name mdrive2
Device, Speed (SpeedFile Version) XC9572, -15 (3.0)
Date Created Wed Jun 13 19:32:55 2012
Created By Timing Report Generator: version L.33
Copyright Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 18.000 ns.
Max. Clock Frequency (fSYSTEM) 55.556 MHz.
Limited by Cycle Time for CLK
Clock to Setup (tCYC) 18.000 ns.
Pad to Pad Delay (tPD) 15.000 ns.
Clock Pad to Output Pad Delay (tCO) 25.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 18.0 156 156
AUTO_TS_P2P 0.0 25.0 12 12
AUTO_TS_P2F 0.0 3.0 1 1
AUTO_TS_F2P 0.0 22.0 36 36


Constraint: TS1000

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
ADC<0>.Q to ADC<10>.D 0.000 18.000 -18.000
ADC<0>.Q to ADC<11>.D 0.000 18.000 -18.000
ADC<0>.Q to ADC<12>.D 0.000 18.000 -18.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to m1 0.000 25.000 -25.000
CLK to m2 0.000 25.000 -25.000
CLK to m3 0.000 25.000 -25.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to CLK_IBUF/FCLK 0.000 3.000 -3.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
ADC<4>.Q to m3 0.000 22.000 -22.000
ADC<4>.Q to m4 0.000 22.000 -22.000
ADC<5>.Q to m3 0.000 22.000 -22.000



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK 55.556 Limited by Cycle Time for CLK

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
m1 25.000
m2 25.000
m3 25.000
m4 25.000


Clock to Setup Times for Clocks

Clock to Setup for clock CLK
Source Destination Delay
ADC<0>.Q ADC<10>.D 18.000
ADC<0>.Q ADC<11>.D 18.000
ADC<0>.Q ADC<12>.D 18.000
ADC<0>.Q ADC<7>.D 18.000
ADC<0>.Q ADC<8>.D 18.000
ADC<0>.Q ADC<9>.D 18.000
ADC<1>.Q ADC<10>.D 18.000
ADC<1>.Q ADC<11>.D 18.000
ADC<1>.Q ADC<12>.D 18.000
ADC<1>.Q ADC<7>.D 18.000
ADC<1>.Q ADC<8>.D 18.000
ADC<1>.Q ADC<9>.D 18.000
ADC<2>.Q ADC<10>.D 18.000
ADC<2>.Q ADC<11>.D 18.000
ADC<2>.Q ADC<12>.D 18.000
ADC<2>.Q ADC<7>.D 18.000
ADC<2>.Q ADC<8>.D 18.000
ADC<2>.Q ADC<9>.D 18.000
ADC<3>.Q ADC<10>.D 18.000
ADC<3>.Q ADC<11>.D 18.000
ADC<3>.Q ADC<12>.D 18.000
ADC<3>.Q ADC<7>.D 18.000
ADC<3>.Q ADC<8>.D 18.000
ADC<3>.Q ADC<9>.D 18.000
ADC<4>.Q ADC<10>.D 18.000
ADC<4>.Q ADC<11>.D 18.000
ADC<4>.Q ADC<12>.D 18.000
ADC<4>.Q ADC<7>.D 18.000
ADC<4>.Q ADC<8>.D 18.000
ADC<4>.Q ADC<9>.D 18.000
ADC<5>.Q ADC<10>.D 18.000
ADC<5>.Q ADC<11>.D 18.000
ADC<5>.Q ADC<12>.D 18.000
ADC<5>.Q ADC<7>.D 18.000
ADC<5>.Q ADC<8>.D 18.000
ADC<5>.Q ADC<9>.D 18.000
ADC<6>.Q ADC<10>.D 18.000
ADC<6>.Q ADC<11>.D 18.000
ADC<6>.Q ADC<12>.D 18.000
ADC<6>.Q ADC<7>.D 18.000
ADC<6>.Q ADC<8>.D 18.000
ADC<6>.Q ADC<9>.D 18.000
ADD<0>.Q ADD<10>.D 18.000
ADD<0>.Q ADD<11>.D 18.000
ADD<0>.Q ADD<12>.D 18.000
ADD<0>.Q ADD<7>.D 18.000
ADD<0>.Q ADD<8>.D 18.000
ADD<0>.Q ADD<9>.D 18.000
ADD<1>.Q ADD<10>.D 18.000
ADD<1>.Q ADD<11>.D 18.000
ADD<1>.Q ADD<12>.D 18.000
ADD<1>.Q ADD<7>.D 18.000
ADD<1>.Q ADD<8>.D 18.000
ADD<1>.Q ADD<9>.D 18.000
ADD<2>.Q ADD<10>.D 18.000
ADD<2>.Q ADD<11>.D 18.000
ADD<2>.Q ADD<12>.D 18.000
ADD<2>.Q ADD<7>.D 18.000
ADD<2>.Q ADD<8>.D 18.000
ADD<2>.Q ADD<9>.D 18.000
ADD<3>.Q ADD<10>.D 18.000
ADD<3>.Q ADD<11>.D 18.000
ADD<3>.Q ADD<12>.D 18.000
ADD<3>.Q ADD<7>.D 18.000
ADD<3>.Q ADD<8>.D 18.000
ADD<3>.Q ADD<9>.D 18.000
ADD<4>.Q ADD<10>.D 18.000
ADD<4>.Q ADD<11>.D 18.000
ADD<4>.Q ADD<12>.D 18.000
ADD<4>.Q ADD<7>.D 18.000
ADD<4>.Q ADD<8>.D 18.000
ADD<4>.Q ADD<9>.D 18.000
ADD<5>.Q ADD<10>.D 18.000
ADD<5>.Q ADD<11>.D 18.000
ADD<5>.Q ADD<12>.D 18.000
ADD<5>.Q ADD<7>.D 18.000
ADD<5>.Q ADD<8>.D 18.000
ADD<5>.Q ADD<9>.D 18.000
ADD<6>.Q ADD<10>.D 18.000
ADD<6>.Q ADD<11>.D 18.000
ADD<6>.Q ADD<12>.D 18.000
ADD<6>.Q ADD<7>.D 18.000
ADD<6>.Q ADD<8>.D 18.000
ADD<6>.Q ADD<9>.D 18.000
ADC<0>.Q ADC<1>.D 10.500
ADC<0>.Q ADC<2>.D 10.500
ADC<0>.Q ADC<3>.D 10.500
ADC<0>.Q ADC<4>.D 10.500
ADC<0>.Q ADC<5>.D 10.500
ADC<0>.Q ADC<6>.D 10.500
ADC<10>.Q ADC<11>.D 10.500
ADC<10>.Q ADC<12>.D 10.500
ADC<11>.Q ADC<12>.D 10.500
ADC<1>.Q ADC<2>.D 10.500
ADC<1>.Q ADC<3>.D 10.500
ADC<1>.Q ADC<4>.D 10.500
ADC<1>.Q ADC<5>.D 10.500
ADC<1>.Q ADC<6>.D 10.500
ADC<2>.Q ADC<3>.D 10.500
ADC<2>.Q ADC<4>.D 10.500
ADC<2>.Q ADC<5>.D 10.500
ADC<2>.Q ADC<6>.D 10.500
ADC<3>.Q ADC<4>.D 10.500
ADC<3>.Q ADC<5>.D 10.500
ADC<3>.Q ADC<6>.D 10.500
ADC<4>.Q ADC<5>.D 10.500
ADC<4>.Q ADC<6>.D 10.500
ADC<5>.Q ADC<6>.D 10.500
ADC<7>.Q ADC<10>.D 10.500
ADC<7>.Q ADC<11>.D 10.500
ADC<7>.Q ADC<12>.D 10.500
ADC<7>.Q ADC<8>.D 10.500
ADC<7>.Q ADC<9>.D 10.500
ADC<8>.Q ADC<10>.D 10.500
ADC<8>.Q ADC<11>.D 10.500
ADC<8>.Q ADC<12>.D 10.500
ADC<8>.Q ADC<9>.D 10.500
ADC<9>.Q ADC<10>.D 10.500
ADC<9>.Q ADC<11>.D 10.500
ADC<9>.Q ADC<12>.D 10.500
ADD<0>.Q ADD<1>.D 10.500
ADD<0>.Q ADD<2>.D 10.500
ADD<0>.Q ADD<3>.D 10.500
ADD<0>.Q ADD<4>.D 10.500
ADD<0>.Q ADD<5>.D 10.500
ADD<0>.Q ADD<6>.D 10.500
ADD<10>.Q ADD<11>.D 10.500
ADD<10>.Q ADD<12>.D 10.500
ADD<11>.Q ADD<12>.D 10.500
ADD<1>.Q ADD<2>.D 10.500
ADD<1>.Q ADD<3>.D 10.500
ADD<1>.Q ADD<4>.D 10.500
ADD<1>.Q ADD<5>.D 10.500
ADD<1>.Q ADD<6>.D 10.500
ADD<2>.Q ADD<3>.D 10.500
ADD<2>.Q ADD<4>.D 10.500
ADD<2>.Q ADD<5>.D 10.500
ADD<2>.Q ADD<6>.D 10.500
ADD<3>.Q ADD<4>.D 10.500
ADD<3>.Q ADD<5>.D 10.500
ADD<3>.Q ADD<6>.D 10.500
ADD<4>.Q ADD<5>.D 10.500
ADD<4>.Q ADD<6>.D 10.500
ADD<5>.Q ADD<6>.D 10.500
ADD<7>.Q ADD<10>.D 10.500
ADD<7>.Q ADD<11>.D 10.500
ADD<7>.Q ADD<12>.D 10.500
ADD<7>.Q ADD<8>.D 10.500
ADD<7>.Q ADD<9>.D 10.500
ADD<8>.Q ADD<10>.D 10.500
ADD<8>.Q ADD<11>.D 10.500
ADD<8>.Q ADD<12>.D 10.500
ADD<8>.Q ADD<9>.D 10.500
ADD<9>.Q ADD<10>.D 10.500
ADD<9>.Q ADD<11>.D 10.500
ADD<9>.Q ADD<12>.D 10.500


Pad to Pad List

Source Pad Destination Pad Delay
CWCCW m1 15.000
CWCCW m2 15.000
CWCCW m3 15.000
CWCCW m4 15.000
PWM m1 15.000
PWM m2 15.000
PWM m3 15.000
PWM m4 15.000


Number of paths analyzed: 205
Number of Timing errors: 205
Analysis Completed: Wed Jun 13 19:32:55 2012